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Design and simulation of a torus structure and route algorithm for network on chip

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3 Author(s)
Chang Wu ; Univ. of Electron. Sci. & Technol. of China, Chengdu ; Yubai Li ; Song Chai

With the development of VDSM, the rising scale and complexity of system-on-chip induce significant communication challenges in bus based architectures. The interconnect delay and unpredictable delay are gradually becoming the bottle neck of increasing complexity for on-chip systems. Current NOC (network on chip) provides an effective solution to these communication problems. In this paper, we study the Torus topology and bring forward a structure for NOC. Besides, we propose a dead-lock and live-lock free route algorithm. During the simulation, we found that our structure and algorithm are superior in hotspot traffic pattern. Furthermore, latency time and throughput of Torus NOC we designed have been tremendously improved comparing with XY Mesh structure.

Published in:

ASIC, 2007. ASICON '07. 7th International Conference on

Date of Conference:

22-25 Oct. 2007