A network-on-Chip system-level simulation environment supporting asynchronous router

Use of asynchronous packet-switching routers in network on chip (NoC) provides better network performance in terms of low minimum latency, power consumption and high average throughput. Since asynchronous mode of operation cannot be naturally simulated in high level language which is implicitly synchronous, one has to resort to RTL modeling where physical delay can be accounted for. With complexity expected in NoC design, this method will be very time consuming. This paper presents a system-level simulation environment that overcomes this dilemma. The simulation framework introduced some special methods to enable the fast simulation of the asynchronous transfer communication. It can be configured to support most asynchronous NoC networks and also handles various communication resources. In all, it simplifies the design flow of an asynchronous NoC design.