Referenced Items are not available for this document.
Demand for techniques to reduce verification time has been increasing in recent VLSI designs using sub-micron processes. The model order reduction (MOR) method by M.Celik et al. (2002) shortens verification time by reducing transfer functions order of the circuits. Employing the MOR method, we have developed a technique to analyze large scale power supply wirings of a whole DSP LSI chip. We have confirmed that our technique greatly improves circuit analysis capability maintaining sufficient accuracy.
Published in:
ASIC, 2007. ASICON '07. 7th International Conference on
Date of Conference: 22-25 Oct. 2007
- Page(s):
- 1186 - 1189
- E-ISBN :
- 978-1-4244-1132-0
- Print ISBN:
- 978-1-4244-1132-0
- INSPEC Accession Number:
- 9808242
- Conference Location :
- Guilin
- Digital Object Identifier :
- 10.1109/ICASIC.2007.4415846
- Product Type:
- Conference Publications
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