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This paper presents a sequential equivalence checking (SEC) framework based upon Boolean satisfiability (SAT) related engines such as sequential SAT and invariant checking. By detecting invariants in the miter circuits, the search space can be dramatically reduced. Some techniques such as timeframe expansion and dynamic candidate selection are introduced to enhance the invariant checking accuracy. Furthermore, a heuristic is presented to quickly find counter-examples for those in-equivalent tasks. The efficiency of the approach is demonstrated using some larger ISCAS89 circuits and hard-to-verify industrial circuits.
ASIC, 2007. ASICON '07. 7th International Conference on
Date of Conference: 22-25 Oct. 2007