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Performance maximized interlayer via planning for 3D ICs

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3 Author(s)
Jun Lu ; Graduate School of IPS, Waseda University, Kitakyushu, Japan ; Song Chen ; Takeshi Yoshimura

As the development of semiconductor industry, 3D IC technology is introduced for its advantages in alleviating the interconnect problem coming with decreasing feature size and increasing integrated density. In 3D IC fabrication, one of the key challenges is the vertical connections between different device layers, which can be implemented by interlayer vias. In this paper, we proposed a performance-maximized interlayer via planning method for 3D ICs (multiple device layers), which can be used in the post-floorplanning stage.

Published in:

2007 7th International Conference on ASIC

Date of Conference:

22-25 Oct. 2007