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-In this paper, we have presented the hardware design implementation of crypto-based Viterbi encoder and decoder using turbo codes. Our design is based on 2/3 bit rate for a constraint length of 3. The turbo encoder has been designed with shift register, modulo-2 adder, TDES (triple-data encryption standard) interleaver. Viterbi decoder section includes convolutional decoder and TDES interleaver and TDES de-interleaver. The results of simulation are obtained from Modelsim 5.8c and the design has been implemented on Spartan2 FPGA using Xilinx 5.1i. The estimated operating frequency for our design was 94.5 MHz which is similar to the existing Block Interleaver using the synthesis tool Leonardo Spectrum 2004.1b.
ASIC, 2007. ASICON '07. 7th International Conference on
Date of Conference: 22-25 Oct. 2007