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A parallel co-processor architecture for block cipher processing

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3 Author(s)
Xue-rong Yu ; Inf. Eng. Univ., Zhengzhou ; Zi-bin Dai ; Xiao-hui Yang

Based on analyzing the operation character of block ciphers, we set forth a solution for efficient cryptographic processing, and put forward a parallel co-processor architecture for block ciphers , which supports word and sub-word parallel processing, and its micro realization is schemed out too. The design gives attention to two aspects which is flexibility and high performance, including consummate control capability, efficient operation capability, and reconfigurable cipher process capability. Finally, in synthesis, the design is fabricated on 0.18um CMOS cells through design compiler tool, and the performance of this co-processor is compared to other hardware/software implementation.

Published in:

ASIC, 2007. ASICON '07. 7th International Conference on

Date of Conference:

22-25 Oct. 2007