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This work proposes the implementation of an energy efficient application specific matrix processor for speech enhancement in noisy speech recognition applications. This implementation considers speech enhancement through signal subspace based speech enhancement algorithm based on Frobenius norm constrained Singular Value Decomposition. The Singular Value Decomposition unit is used in time multiplexed fashion to perform noise reduction during feature extraction stage and it is also used for matrix inversion of the block diagonal covariance matrices for the final speech recognition block. This processor along with a 4 state Continuous Hidden Markov Model based hardware speech recognizer achieves a recognition performance improvement of 5% in noisy environments. Word samples from AN4 database is used to test the speech recognizer which has got a recognition accuracy of 96.8%. The FPGA prototyping of the above noise enhancement algorithm using the ASIP accelerator was carried out in Altera FPGA with NIOS processor.
ASIC, 2007. ASICON '07. 7th International Conference on
Date of Conference: 22-25 Oct. 2007