A high efficient analog charge delay line for high performance CMOS readout integrated circuits with TDI function

A high efficient analog charge delay line (ACDL) is proposed in this paper. We can use these analog delay lines to realize high performance CMOS readout integrated circuits (ROIL with time delay integration (TDI) function. A CMOS ROIC for 288 X 4 IRFPA were designed, manufactured, and tested. The chip has 4 video outputs, whose pixel frequency is 4˜5MHz (for 384X 288 format, its frame frequency can achieve 160Hz). Test results show this chip has high dynamic range (>MB), high linearity (>99.5%), and high uniformity (96.8%).