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This paper presents an equalization-based digital background error-correction technique for successive approximation analog-to-digital converters (SA-ADCs). Computer simulation indicates that large differential and integral nonlinearities resulting from component errors including capacitor mismatch, comparator offset, and switch-induced offset can be corrected in the digital domain by an FIR adaptive filter, which essentially performs a linear equalization (LE) to align the digital codes of the SA-ADC to those of a slow-but-accurate reference ADC. In return, the size of the sampling capacitors can be scaled down to the kT/C limit without matching concerns. For SA-ADCs with resolutions of 10 bits and above, a large power saving is envisioned using the proposed low-cost, power-efficient digital calibration technique. The treatment improves the scalability and power efficiency of SA-ADCs in deeply scaled CMOS technology.