By Topic

An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Wenbo Liu ; Univ. of Illinois at Urbana-Champaign, Urbana ; Yun Chiu

This paper presents an equalization-based digital background error-correction technique for successive approximation analog-to-digital converters (SA-ADCs). Computer simulation indicates that large differential and integral nonlinearities resulting from component errors including capacitor mismatch, comparator offset, and switch-induced offset can be corrected in the digital domain by an FIR adaptive filter, which essentially performs a linear equalization (LE) to align the digital codes of the SA-ADC to those of a slow-but-accurate reference ADC. In return, the size of the sampling capacitors can be scaled down to the kT/C limit without matching concerns. For SA-ADCs with resolutions of 10 bits and above, a large power saving is envisioned using the proposed low-cost, power-efficient digital calibration technique. The treatment improves the scalability and power efficiency of SA-ADCs in deeply scaled CMOS technology.

Published in:

ASIC, 2007. ASICON '07. 7th International Conference on

Date of Conference:

22-25 Oct. 2007