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A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders

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4 Author(s)
Chi-Hong Chan ; Chinese Univ. of Hong Kong, Shatin ; Cheong-Fat Chan ; Chiu-Sing Choy ; Kong-Pang Pun

This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDR SFDR and THD of 65.17 dB, 73.89d B and -73.26 dB at 2.5V supply voltage and 50 MHz sampling rate.

Published in:

ASIC, 2007. ASICON '07. 7th International Conference on

Date of Conference:

22-25 Oct. 2007