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A 10-b 80Ms/s time-interleaved pipeline ADC using partially opamp sharing Scheme

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4 Author(s)
Cao Junmin ; Institute of Microelectronics, Peking University, Beijing 100871, China ; Chen Zhongjian ; Lu Wengao ; Zhao Baoying

A 10-bit 80 MS/s two-channel time-interleaved pipeline analog-digital converter is presented. Nonlinearity and Mismatch between the channels are minimized by applying partially opamp sharing scheme. And a dedicated double-sampling SHA is employed to eliminate time skew between the channels. The converter architecture is also optimized for power dissipation by employing dynamic comparator and stage scaling down technology. Simulated with 0.5 um technology, the ADC dissipates 210 mw of power from a 5 v supply, and achieves a peak SNDR of 56 dB at 80 Ms/s.

Published in:

2007 7th International Conference on ASIC

Date of Conference:

22-25 Oct. 2007