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Research and implement a low-power configurable embedded processor for 1024-point fast fourier transform

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4 Author(s)
Yong Li ; School of Computer, National University of Defense Technology, Hunan Changsha 410073, China ; Zhi-ying Wang ; Jian Ruan ; Kui Dai

The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In TTA processors, the special function units can be utilized to increase performance or reduce power dissipation. This paper presents a low-power TTA processor using hybrid asynchronous and synchronous function units. This processor is customized for a 1024-point FFT application. We also implement a processor only using synchronous function units. Comparing to the synchronous processor core, the processor core using asynchronous function units has lower average power dissipation and higher performance.

Published in:

2007 7th International Conference on ASIC

Date of Conference:

22-25 Oct. 2007