ASIC design of low-power reconfigurable FFT processor

An improved ASIC design of a low power reconfigurable FFT processor for handling high speed digital signal is proposed. Radix 2-4-4-8-8 pipeline structure is chosen to achieve low complexity of hardware and high reconfigurable flexibility. The improved data access makes pipeline architecture be reconfigured as 64,128, 256, 512,1024 or 2048 points computation. By optimizing the pipeline of complex multiplication and power consumption, the method based on CORDIC algorithm are adopted to achieve a low-power FFT processor and results in a substantial savings in hardware resources and the amount of delay elements. The ASIC design is synthesized, placed and routed using Synopsys with SMIC CMOS 0.18μm library. Compared to other designs, this design succeeds in arriving at the goal of high speed, low power and reconfigurablility.