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Topics Covered With CMOS quick scaling down, more and more components are integrated into a SOC chip. How to design a complex SOC chip is becoming a very challenging topic. In this tutorial, we will use our design experience on a video processing pipeline to illustrate the complete design flow for a SOC system. A video processing pipeline consists video signal demodulation, video decoding (H.264/MPEG2/MPEG4 /VC1/AVS, etc), and video post-processing, etc. For video post-processing, it is designed to enhance video quality and might contain motion adaptive/compensated de-interlacing, motion compensated frame rate conversion, noise reduction (out-loop de-blocking, de-ringing, mosquito noise and Gaussian noise reducer), contrast enhancement, sharpness enhancement, color enhancement, etc. There are several reasons that we choose this video processing pipeline as an illustrative example. By year 2006, the consumer electronics market already achieved size of $145 billion, and it will grow to more than $155 billion in 2007, according to the semi-annual industrial report released by the Consumer Electronics Association (CEA). The transition from analog to digital television together with the dramatic price fall of LCD panel/plasma display will fuel demand in the television market and display technologies to totally account for $26 billion. There are three important factors in making a digital television. The first is panel manufacturing; the second is the semiconductor chip supporting video processing; and the third is component assembling. Among them, video processing pipeline is the core of a digital television and the most design-intensive factor. Further, this video processing pipeline is a very important component inside high-end Graphics Processing Unit (GPU) as implemented and demonstrated in AMD/ATI All-in-Wonder X1900, NVIDIA GPU with Pure Video technology, and Intel integrated/discrete GPU. In this tutorial, we will cover most issues related with designing a SOC for- video processing pipeline. More specifically, we will focus our discussion on how to design the algorithms, architecture, and register-transfer level implementation for video post processing. Furthermore, we will discuss the FPGA prototype of this video processing pipeline, and chip validation flow based on simulation and emulation. Target audience This tutorial is intended to provide an insight view on video processing pipeline for industry and academia architects, ASIC/SOC designers, validation engineers, etc. Since this tutorial will bring an industry design experience on a complex SOC system and cover a complete design flow from algorithm, architecture, RTL, FPGA prototype, and chip validation, it will benefit a substantial part of the ASICON2007 audience if they attend this tutorial. Prerequisite knowledge Basic knowledge on video, VLSI, and computer architecture is recommended.