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A new scalable compact model for the resistive substrate network of multi-finger MOSFETs is presented. The model is based on the transmission line formalism to capture the distributed nature of the well resistance. Due to its physical foundation, the model provides a more accurate description of different layout styles over a wide range of geometries. The model is validated experimentally on a 90 nm CMOS technology and is used to determine the geometry of RF transistors that minimize the substrate resistance. The opted network topology allows a direct implementation with the PSP model.