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High-Voltage-Tolerant I/O Circuit Design for USB 2.0-Compliant Applications

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4 Author(s)
Moon-Jung Kim ; Stanford Univ., Stanford ; Icking, H. ; Gossner, H. ; Lee, T.H.

We present design strategies of high-voltage tolerant I/O circuits for interfaces of 3.3 V or higher. The test vehicle is a USB 2.0-compliant I/O circuit. This is a challenging example because USB 2.0 requires substantial over-voltage tolerance from -IV to 5.25 V. In addition, USB 2.0 requires continuous monitoring of this condition and protection when no power is present. The proposed concept is demonstrated in a 90 nm CMOS process.

Published in:

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Date of Conference:

16-19 Sept. 2007