Referenced Items are not available for this document.
A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.
Published in:
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Date of Conference: 16-19 Sept. 2007
- Page(s):
- 459 - 462
- E-ISBN :
- 978-1-4244-1623-3
- Print ISBN:
- 978-1-4244-0786-6
- INSPEC Accession Number:
- 9803863
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/CICC.2007.4405773
- Product Type:
- Conference Publications
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