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A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS

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3 Author(s)
Darabiha, A. ; Toronto Univ., Toronto ; Carusone, A.C. ; Kschischang, F.R.

A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm2 core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.

Published in:

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Date of Conference:

16-19 Sept. 2007