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A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS

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2 Author(s)
Bogue, I. ; Michigan Univ., Ann Arbor ; Flynn, M.P.

A digitally calibrated 8-bit folding ADC incorporating redundancy and reassignment is described. Small, redundant folder and comparator circuits generate 1024 available zero-crossings. An entirely self-contained calibration engine selects 255 zero-crossings from the available set. Unselected circuits are powered down. The calibration breaks the link between ADC performance and analog accuracy, allowing small transistors to be used in the signal path. Fabricated in 0.18 μm digital CMOS, the DNL of the uncalibrated ADC is 6.7 LSB and 0.8 LSB, before and after calibration, respectively. SFDR remains above 55 dB up to a sampling rate of 550 MS/s. The total die area is 1.2mm2.

Published in:

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Date of Conference:

16-19 Sept. 2007