Referenced Items are not available for this document.
A low-power small-area single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS is presented. The entire ADC is implemented using CML blocks. To enhance the speed, both analog (comparators) and digital (encoder) parts of the ADC are fully pipelined. Furthermore, a reformulation for the encoder logic functions is introduced to reduce the wiring delay in the layout. The ADC achieves a figure of merit of 2.14 pJ/conversion-step. The ADC area including the resistor ladder is 0.06 mm2 and the power consumption is 43 mW when supplied with 1.8 V.
Published in:
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Date of Conference: 16-19 Sept. 2007
- Page(s):
- 333 - 336
- E-ISBN :
- 978-1-4244-1623-3
- Print ISBN:
- 978-1-4244-0786-6
- INSPEC Accession Number:
- 9816890
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/CICC.2007.4405746
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