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A 10-Gb/s receiver for chip-to-chip communication is presented which employs an eye-opening monitor for both adaptive equalization as well as digital clock and data recovery (CDR). The prototype circuit fabricated in 0.13-mum CMOS technology consumes about 164 mW (adaptive equalizer and CDR, excluding output buffers) at 1.2 V supply voltage and occupies about 0.39 times 0.39 mm2. The CDR fulfills the SONET/SDH jitter tolerance requirements at a 231-1 PRBS and a BER of < 10-12. Successful adaptive equalization of a 30 cm (12") and 76 cm (30") channel on standard FR4 substrate is also demonstrated.