By Topic

A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yi-Chung Chen ; Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan ; Yi-Chang Wu ; Po-Chiun Huang

This paper presents low-voltage low-power limiter, RSSI, and demodulator designs for a low-IF wireless FSK receiver. The IF is located at 3 MHz. The FSK demodulator is implemented by a delay-locked loop associated with the techniques of digital offset cancellation and modified phase-frequency detection. The demodulated data can be recovered with one-clock latency. The circuits in limiter and RSSI are all pseudo differential to minimize the requirement of the voltage headroom. Each gain cell with feedforward offset cancellation and common mode stabilization circuits can make sure its functionality against device mismatch. The chip uses a standard 0.18 mum CMOS process. The active area is 0.11 mm2. With a single 1.2-V power supply, measurement results show that the 55 dB gain, 15 MHz bandwidth limiter and the RSSI consume 1.9 mA. The FSK demodulator part consumes 300 muA.

Published in:

2007 IEEE Custom Integrated Circuits Conference

Date of Conference:

16-19 Sept. 2007