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A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone Calibration

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2 Author(s)
Yangjin Oh ; Department of Electrical Engineering, Stanford University, Stanford, CA 94305 ; Boris Murmann

A low-power analog-to-digital converter (ADC) that exploits communication system resources for continuous self-calibration is presented. The proposed converter employs a time-interleaved array of successive approximation register (SAR) ADCs. The inter-channel offset mismatches are adjusted by a calibration loop that utilizes the outputs of the fast Fourier transform (FFT) block of an orthogonal frequency division multiplexing (OFDM) receiver. The 6-bit prototype ADC, fabricated in a 0.18-mum CMOS technology, achieves an SNDR of 35.4 dB with a power consumption of 6.58 mW at 200 MS/s.

Published in:

2007 IEEE Custom Integrated Circuits Conference

Date of Conference:

16-19 Sept. 2007