By Topic

Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

11 Author(s)

A highly scalable flash-based Field Programmable Gate Array (FPGA) technology has been achieved with Deep Trench Isolation (DTI). The DTI allows for a reduced cell size and enables Independent Pwell (IPW) operation. The IPW allows the Fowler-Nordheim (FN) Uniform Channel Program and Erase (UCPE) with less than plusmn10 V. Additionally, the IPW approach allows a greater flexibility in the array bias scheme reducing the gate disturb during programming and eliminating all Gate-Induced Drain Leakage (GIDL) conditions. Characterization of a FPGA cell and 0.5 Mbit array with 90 nm design rules is demonstrated with excellent electrical characteristics.

Published in:

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Date of Conference:

16-19 Sept. 2007