By Topic

A Delta-Sigma Modulator with a Widely Programmable Center Frequency and 82-dB Peak SNDR

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yamamoto, K. ; Toronto Univ., Toronto ; Carusone, A.C. ; Dawson, F.P.

A. 4-bit fourth-order delta-sigma modulator with a widely programmable center frequency is presented. Novel methods for quantizing and implementing the digitally programmable modulator coefficients enable performance comparable to state-of-the-art discrete-time fixed-frequency modulators at any center frequency from dc to 0.31 fs in steps of 0.0052/s. The 0.18-mum 1.8-V CMOS prototype consumes 115 mW at a sampling frequency of 40 MHz. The peak SNDR and SNR over a 310-kHz bandwidth are 82 dB and 86 dB respectively.

Published in:

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Date of Conference:

16-19 Sept. 2007