By Topic

Characterization, Modeling and Extraction of Cu Wire Resistance for 65 nm Technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)

We present an innovative and comprehensive approach to characterize and model interconnect wire resistance. We have measured Cu wire resistance for fully processed 10 BEOL Cu levels in IBM high performance 65 nm technologies, and analyzed resistance data for multiple wire widths at multiple temperatures. Combined with the SEM cross-section data of a few measured Cu wire structures, we have successfully extracted all parameters of a Spice model for the 65 nm node interconnect resistance. The extracted Spice wire resistance model includes the congregated effects of surface scattering, grain boundary scattering and surface roughness in IBM 65 nm BEOL technology. New behavior of wire resistance is reported for the first time.

Published in:

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Date of Conference:

16-19 Sept. 2007