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Canary bitcells act as online monitors in a feedback architecture to sense the proximity to the data retention voltage (DRV) for core SRAM bitcells during standby voltage scaling. This approach implements aggressive standby VDD scaling by tracking PVT variations and gives the flexibility to tradeoff between the safety of data and decreased leakage power. A 90 nm 128 Kb SRAM test chip confirms that the canary cells track changes in temperature and VDD and that they provide a reliable mechanism for protecting core cells in a closed loop VDD scaling system. Power savings improve by up to 30times compared with the conventional guard-banding approach.