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This paper presents a novel 8 transistor SRAM cell that can be used for enhancing cell Vddmin at and beyond 90 nm technology nodes. This cell provides a way to eliminate the column select read disturb scenario in SRAMs which is one of the impediments to lowering cell voltage. Read disturbs to the selected cell are then minimized by relying on a sense-amp based array architecture which enables discharging the bit-line (BL) capacitance to GND during a read operation thereby enhancing its low voltage operability. The sensitivity of the cell to BL height and sense timing has been studied and the feasibility of the cell has been proved by fabricating a 32 Kb array in a 90 nm PD/SOI technology. Hardware experiments and simulation results show improvements of cell Vddmin over traditional 6T cells by more than 150 mV for 90 nm PD/SOI technology.