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A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs

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3 Author(s)
Giri, C. ; Dept of E & ECE, HT Kharagpur, India ; Sarkar, Soumojit ; Chattopadhyay, S.

This paper presents a Genetic algorithm (GA) based solution to co-optimize test scheduling and wrapper design under power constraints for core based System-On-Chips (SOCs). Core testing solutions are generated as a set of wrapper configurations, represented as rectangles with width equal to the number of TAM (Test Access Mechanism) channels and height equal to the corresponding testing time. A locally optimal best-fit heuristic based bin packing algorithm has been used to determine placement of rectangles minimizing the overall test times, whereas, GA has been utilized to generate the sequence of rectangles to be considered for placement. Experimental result on ITC’02 benchmark SOCs shows that the proposed method provides better test time results compared to the recent works reported in the literature.

Published in:

Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on

Date of Conference:

15-17 Oct. 2007

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