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A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes

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4 Author(s)
Rovini, M. ; Department of Information Engineering - University of Pisa Via G. Caruso, 1-56122 - Italy ; Gentile, G. ; Rossi, F. ; Fanucci, L.

This paper describes a scalable architecture of a decoder for IEEE 802.11n low-density parity-check (LDPC) codes. The decoder runs the layered decoding algorithm and its architecture is arranged in clusters of serial functional units, which are configured to process all codes in the standard. The decoder works in pipeline, and a very effective technique to re- arrange the sequence of its elaborations is proposed in order to minimize the iteration latency; this relates to the order of the messages input and output by the processing units, as well as the sequence of layers followed for decoding. Moreover, memory optimization techniques have been applied to get a very efficient partitioning, allowing the pipeline of the operations. The synthesis on 65 nm CMOS technology with low-power standard- cell library, shows that the proposed design is suitable for portable devices, the throughput ranging from 136 to 355 Mbps, and the power consumption being below 185 mW.

Published in:

Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on

Date of Conference:

15-17 Oct. 2007