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Evaluating memory sharing data size and TCP connections in the performance of a reconfigurable hardware-based architecture for TCP/IP stack

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3 Author(s)
Hamerski, Jean Carlo ; Universidade Federal do Rio Grande do Sul Instituto de Informática - PPGC Porto Alegre - Brazil ; Reckziegel, Everton ; Kastensmidt, F.L.

The TCP/IP (Transmission Control Protocol/Internet Protocol) Stack processing based on software becomes a bottleneck for the explosive growth of data transmission rate on the Internet. Software- based TCP/IP is not able to process the packets at the same rate of transmission lines, which has been pushing the TCP/IP processing implementation into hardware. The use of dedicated hardware for TCP/IP stack processing aims reducing the Central Unit Processing (CPU) load and increase as possible the throughput for Internet services that need a large bandwidth. In this way, a reconfigurable hardware-based architecture to transport and network layers protocols processing is proposed. The effect of shared memory data size and the number of TCP connections were evaluated in terms of area and packets computation performance.

Published in:

Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on

Date of Conference:

15-17 Oct. 2007

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