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An efficient H.264 intra frame coder system design

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3 Author(s)
Ilker Hamzaoglu, ; Faculty of Engineering and Natural Sciences, Sabanci University 34956, Tuzla, Istanbul, Turkey ; Tasdizen, O. ; Esra Sabin,

In this paper, we present an efficient H.264 / MPEG4 Part 10 Intra Frame Coder System. The system achieves real-time performance for portable applications with low hardware cost, and it includes a novel intra prediction hardware design. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code works at 71 MHz in a Xilinx Virtex II FPGA and it code 35 CIF frames (352×288) per second. The system also includes a software running on an Arm926EJS processor for implementing pre-processing and post-processing functions. The H.264 Intra Frame Coder hardware and software are demonstrated to work together on an Arm Versatile Platform development board.

Published in:

Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on

Date of Conference:

15-17 Oct. 2007

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