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Verifying Correctness of Transactional Memories

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5 Author(s)

We show how to verify the correctness of transactional memory implementations with a model checker. We show how to specify transactional memory in terms of the admissible interchange of transaction operations, and give proof rules for showing that an implementation satisfies this specification. This notion of an admissible interchange is a key to our ability to use a model checker, and lets us capture the various notions of transaction conflict as characterized by Scott. We demonstrate our work using the TLC model checker to verify several well-known implementations described abstractly in the TLA+ specification language.

Published in:

Formal Methods in Computer Aided Design, 2007. FMCAD '07

Date of Conference:

11-14 Nov. 2007