By Topic

Do we expect ESD failures in an EPA designed according to international standards? The need for a process related risk analysis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Gaertner, R. ; Infineon Technol., Munich

ESD failures can occur in ESD protected areas that are designed according to the latest ESD standards like ANSI S20.20 or IEC 61340-5-1. The root cause for the failures can normally only be found by a detailed analysis of the whole production flow. This paper shows what hazards for ESD damages can occur in a typical process flow of a typical PCB manufacturing line, how the risk is going to be analyzed, and how it can be minimized. This method will be explained with some examples from the field.

Published in:

29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD

Date of Conference:

16-21 Sept. 2007