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Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations

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3 Author(s)
Ness, D.C. ; Univ. of Minnesota, Minneapolis ; Hescott, C.J. ; Lilja, D.J.

One of the key challenges in nanoelectronics design is the decreasing reliability due to radiation induced single-event upsets. Without detailed device level simulations or physical experimentation, circuit level models can generate misleading reliability information. We present the results from a screening experiment to identify significant parameters in circuit level SEU simulations. We show that cell supply voltage, sizing parameters, and transient waveform descriptions have an important impact on design and should therefore be considered with care in circuit level designs. Larger variations in parameters can lead to soft error rate estimates that vary by more than 4 orders of magnitude, even small variations can lead to 15times variation in soft error rate estimation for a design. We present our methodology for screening and a ranking based on significance of several parameters involved in soft error simulation at the SPICE level.

Published in:

Nanoscale Architectures, 2007. NANOSARCH 2007. IEEE International Symposium on

Date of Conference:

21-22 Oct. 2007