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A fast, numerical circuit-level model of carbon nanotube transistor

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3 Author(s)
Kazmierski, T.J. ; Sch. of Electron. & Comput. Sci., Southampton Univ., Southampton ; Dafeng Zhou ; Al-Hashimi, B.M.

Recently proposed circuit-level models of carbon nanotube transistor (CNT) for SPICE-like simulators suffer from numerical complexities as they rely on numerical evaluation of integrals or internal Newton-Raphson iterations to find solutions of non-linear dependencies or both. Recently an approach has been proposed which eliminates the need for numerical integration when calculating the charge densities in CNT through the use of piece-wise linear approximation. This paper extends the effective employment of numerical piece-wise approximation to the solution of the Fermi-Dirac integral to accelerate the CNT model speed when evaluating the source-drain current while maintaining high modeling accuracy. Our results show a speed up of more than three orders of magnitude compared with the theoretical CNT model implemented in FETToy, used as a reference for verifying newer models. Comparisons of drain-source current characteristics of the new model against that in FETToy are presented, confirming that the accuracy of the proposed approach is maintained within less than 5% in terms of RMS error.

Published in:

Nanoscale Architectures, 2007. NANOSARCH 2007. IEEE International Symposium on

Date of Conference:

21-22 Oct. 2007