By Topic

[Copyright notice]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.

The following topics are dealt with: parasitic extraction; variability modeling; networks-on-chip; latency-insensitive systems; power grid analysis; quantum circuits; physical optimization; logic synthesis; memory optimization; 3D integration challenges; SAT application; embedded systems; nano-photonic silicon circuits; formal verification; statistical timing analysis; FPGA; clock design; high level synthesis; analog circuit optimization; global routing; gate level physical synthesis; multilevel interconnect networks; floorplanning; system-level synthesis; interconnect design; Mosfet modeling; variation tolerant circuits; deep submicron technologies; design automation; leakage power reduction; non-linear system.

Published in:

Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on

Date of Conference:

4-8 Nov. 2007