By Topic

A Novel Circuit-Level SEU Hardening Technique for High-Speed SiGe HBT Logic Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)

In this work we present a new circuit-level hardening technique for SEU mitigation in high-speed SiGe BiCMOS digital logic. A reduction in SEU vulnerability is realized through the implementation of an additional storage cell redundancy block to achieve the required decoupling. When compared with latch duplication, current sharing or gated feedback techniques, this method incurs a lower power penalty and no speed penalty. The hardened circuit is implemented in CML and LVL families and circuit simulation models predict significant reduction in the number of upsets compared to the corresponding unhardened versions. The technique is also easy to incorporate into existing designs.

Published in:

IEEE Transactions on Nuclear Science  (Volume:54 ,  Issue: 6 )