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Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic

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6 Author(s)
Amusan, O.A. ; Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN ; Massengill, L.W. ; Bhuva, B.L. ; DasGupta, Sandeepan
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Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.

Published in:

Nuclear Science, IEEE Transactions on  (Volume:54 ,  Issue: 6 )

Date of Publication:

Dec. 2007

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