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In general, considerable time and resources are spent during pre-silicon verification phase to proactively minimize functional issues at first silicon. This is no different on the UltraSPARC T2 - the world's fastest commodity microprocessor. We deployed simulation, formal and emulation technologies coupled with solid methodology to cover all our bases, ensuring functional success of first silicon. A robust post-silicon verification methodology is critical to speeding up time-to-ramp and to prevent loss of product revenue. Formal verification has been deployed as one of the means to root cause silicon failure due to functional error. To ensure correct RTL fix, it is vital to be able to effectively reproduce a failure observed in silicon test and recreate it in RTL environment. One way of getting the RTL failure recreated quickly is by writing the failure scenario in terms of property and using formal tool to generate traces that lead to the failure. In this paper, we describe how simulation, formal and emulation technology coupled with capabilities instrumented in our test generators and RTL for repeatability helped isolate faults, run millions of new verification cycles to validate RTL fixes and formally prove the fixes to be error free. We also share impact of our post-silicon validation strategy on productization schedule of Sun UltraSPARC T2 processor.