By Topic

Techniques to improve motion compensation performance of H264 video decoder using a vector processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yajnanarayana, V. ; Motorola India Electron. Ltd., Bangalore ; Subramaniyan, R. ; Schuette, M.

Motion Compensation for video decoding in standards like H.264 requires significant amount of computation. This is primarily because of H.264 six-tap FIR filtering for sub-sample computation. These algorithms typically take more than 50% of the computational time on a RISC processor like ARM. Novel algorithms proposed through this paper can be employed for systems which use vector processors as video decode accelerators to accelerate this process. The proposed algorithms are implemented on H264 video decode system with ARM9 host-processor and RSVP vector processor as an accelerator for key decode algorithms. By employing the proposed algorithms we were able to accelerate the motion compensation module by more than 4 times as compared to plain RISC implementation. This is achieved by efficiently vectorizing data on which FIR-filtering and reconstruction algorithm is operated on, together with optimal representation of FIR-filtering and reconstruction algorithm itself on vector processor.

Published in:

Communications and Information Technologies, 2007. ISCIT '07. International Symposium on

Date of Conference:

17-19 Oct. 2007