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On Cosimulating Multiple Abstraction-Level System-Level Models

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2 Author(s)
Hiren D. Patel ; Dept. of Electr. & Comput. Engineeing, Virginia Polytech. & State Univ., Blacksburg, VA ; Sandeep K. Shukla

SystemC's growing community for system-level design exploration is a result of SystemC's capability of modeling at register transfer level (RTL) and above RTL abstraction levels. However, a synthesis path from SystemC at abstraction layers above RTL is still in its infancy. A recent extension of SystemC, which is called Bluespec-SystemC electronic system level (BS-ESL), counters this difficulty with its model of computation employing atomic rule-based specifications and synthesis to Verilog. In order to simulate a model consisting of one part designed in SystemC and another using BS-ESL, we require an interoperability semantics and implementation of such a semantics. To illustrate the problem, we formalize the simulation semantics of BS-ESL and discrete-event simulation of RTL SystemC, and provide a solution based on this formalization.

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:27 ,  Issue: 2 )