Referenced Items are not available for this document.
A high-speed low-power correlated double sampling counter for column parallel CMOS imagers is proposed. Unlike a conventional up/down counter, the proposed counter performs correlated double sampling using a two's complement arithmetic. The proposed counter can be implemented using only 16 transistors per bit. Simulation results show 32% reduction of power consumption and 2.4 times improvement of maximum speed over a conventional up/down counter.
Published in:
Electronics Letters
(Volume:43
,
Issue:
24
)
Date of Publication: Nov. 22 2007
- Page(s):
- 1362 - 1364
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 9944896
- Digital Object Identifier :
- 10.1049/el:20072490
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 04 December 2007
- Issue Date :
- Nov. 22 2007
- Sponsored by :
- Institution of Engineering and Technology
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