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This paper presents a built-in self-test (BIST) architecture for testing high-speed analog-to-digital converters (ADCs) with sampling rates in excess of 1 GHz. A methodology for performing mixed-mode BIST simulations is proposed, along with hardware for performing on-chip BIST. The architecture presented utilizes an on-chip read-only memory and allows for the generation of single-frequency as well as multiple frequency test signals. The issues associated with BIST signal generation for low-voltage ADCs are presented. Simulations revealed that the spurious-free dynamic range of the sinusoidal signal generated from the BIST hardware was 25.28 dB with a frequency of 312.5 MHz and 19.88 dB with a frequency of 416.67 MHz. The proposed 8-b segmented current steering digital-to-analog converter was designed by IBM 130-nm complementary metal-oxide-semiconductor process. The effective chip area is 0.51mm2. The design measurement results show a converter rate of 1.25 GHz, a gain bandwidth of 220 MHz, and a consumption of 28.5 mA for a power dissipation of 39.5 mW.