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Power and Area Efficient Column-Parallel ADC Architectures for CMOS Image Sensors

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4 Author(s)
Martijn F. Snoeij ; Electronic Instrumentation Laboratory, DIMES, Delft University of Technology, Delft, The Netherlands; Texas Instruments Deutschland GmbH, Erlangen, Germany. e-mail: M.F.Snoeij@ewi.tudelft.nl ; Albert J. P. Theuwissen ; Johan H. Huijsing ; Kofi A. A. Makinwa

The ever-increasing resolution of CMOS imagers has had a profound impact on their analog readout electronics, and, in particular, on their ADC architecture. This paper gives an overview of the development of column-parallel ADCs that enable the high-speed and power-efficient readout of high-resolution CMOS imagers. In particular, the recently proposed multiple-ramp single-slope (MRSS) ADC will be discussed.

Published in:

Sensors, 2007 IEEE

Date of Conference:

28-31 Oct. 2007