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Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection

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5 Author(s)
Su-Hon Lin ; Graduate School of Engineering Science and Technology, National Yunlin University of Science & Technology, 123 University Road, Section 3, Douliou, Yunlin 64002, Taiwan, g9110807@yuntech.edu.tw ; Ming-hwa Sheu ; Wang, Kuang-Hui ; Zhu, Jun-Jie
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A novel Hybrid-Carry-Selection (HCS) approach used for deriving an efficient modulo 2n-1 addition is presented in this study. Its resulting adder architecture which is mainly built by modified carry look-ahead adder (MCLA), carry prediction unit and simple multiplexer (MUX) is simple and regular for all n values. For VLSI implementation based on 180nm standard-cell technology, the HCS-based modulo 2n-1 adder demonstrates the superiority in AreaxTime (AT) performance over those of the latest existing solutions. The layout area and clock rate for HCS-based 216-1 modular adder chip are 25709 um2 and 518MHz respectively.

Published in:

Signal Processing Systems, 2007 IEEE Workshop on

Date of Conference:

17-19 Oct. 2007