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This paper presents a new low-power memory-efficient trace-back (TB) scheme for high constraint length Viterbi decoder (VD). With the trace-back modifications and path merging techniques, up to 50% memory read operations in the survivor memory unit (SMU) can be reduced. The memory size of SMU can be reduced by 33% and the decoding latency can be reduced by 14%. The simulation results show that compared to the conventional TB scheme, the performance loss of this scheme is negligible.
Published in:
Signal Processing Systems, 2007 IEEE Workshop on
Date of Conference: 17-19 Oct. 2007
- Page(s):
- 132 - 135
- ISSN :
- 1520-6130
- E-ISBN :
- 978-1-4244-1222-8
- Print ISBN:
- 978-1-4244-1222-8
- Conference Location :
- Shanghai, China
- Digital Object Identifier :
- 10.1109/SIPS.2007.4387532
- Product Type:
- Conference Publications
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