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Design of Low-Power Memory-Efficient Viterbi Decoder

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3 Author(s)
Lupin Chen ; School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331, USA, Email: lpchen@eecs.oregonstate.edu ; Jinjin He ; Zhongfeng Wang

This paper presents a new low-power memory-efficient trace-back (TB) scheme for high constraint length Viterbi decoder (VD). With the trace-back modifications and path merging techniques, up to 50% memory read operations in the survivor memory unit (SMU) can be reduced. The memory size of SMU can be reduced by 33% and the decoding latency can be reduced by 14%. The simulation results show that compared to the conventional TB scheme, the performance loss of this scheme is negligible.

Published in:

2007 IEEE Workshop on Signal Processing Systems

Date of Conference:

17-19 Oct. 2007