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Chip Power Model - A New Methodology for System Power Integrity Analysis and Design

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3 Author(s)
Emre Kulali ; Apache Design Solutions, 1098 Alta Avenue, Mountain View, CA 94043. Tel: (650) 641 4219 Fax: (650) 641-5019, emnre@apachc.da.com ; Evgeny Wasserman ; Ji Zheng

A compact SPICE equivalent circuit model of full-chip power network is proposed in this paper to address the system power integrity co-design and optimization. The theory and procedures for the generation of the compact chip power model is described. The accuracy validation of the chip power model is also presented.

Published in:

2007 IEEE Electrical Performance of Electronic Packaging

Date of Conference:

29-31 Oct. 2007