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Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation

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4 Author(s)
Pugliese, A. ; Dept. of Electron., Calabria Univ., Rende ; Amoroso, F.A. ; Cappuccino, G. ; Cocorullo, G.

A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach allows the systematic optimisation of the amplifier time response to be performed avoiding time-consuming trial-and- error design processes. A design example in 0.35 mum CMOS technology is also reported. Circuital and statistical simulations demonstrate the effectiveness of the proposed approach.

Published in:

Electronics Letters  (Volume:43 ,  Issue: 23 )

Date of Publication:

Nov. 8 2007

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