By Topic

IEEE 1588 on Windows XP® Powered Measurement Devices - Mastering the Trigger Challenge

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Schmidt, K.U. ; Rohde&Schwarz GmbH & Co. KG, Munich

In the literature, one can find many recommendations for clock designs for either fully HW assisted IEEE 1588 systems or embedded SW implementations. The focus of such solutions is mostly on improving the synchronization performance. However, in most test and measurement systems, the main problem is not synchronization of clocks, but triggering of devices: even on a general purpose OS like Windows XPreg it is always possible to find a clock source with a sufficient resolution of around 1 mus for a SW-only IEEE 1588 implementation, but none of the built-in timers is suitable for triggering the device with such a resolution. In this paper, we will discuss the limits of timers under Windows XPreg and introduce an FPGA based timing HW as assistance for an IEEE 1588 SW implementation for use in Rohde&Schwarz FSL spectrum analyzers.

Published in:

Precision Clock Synchronization for Measurement, Control and Communication, 2007. ISPCS 2007. IEEE International Symposium on

Date of Conference:

1-3 Oct. 2007