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In the literature, one can find many recommendations for clock designs for either fully HW assisted IEEE 1588 systems or embedded SW implementations. The focus of such solutions is mostly on improving the synchronization performance. However, in most test and measurement systems, the main problem is not synchronization of clocks, but triggering of devices: even on a general purpose OS like Windows XPreg it is always possible to find a clock source with a sufficient resolution of around 1 mus for a SW-only IEEE 1588 implementation, but none of the built-in timers is suitable for triggering the device with such a resolution. In this paper, we will discuss the limits of timers under Windows XPreg and introduce an FPGA based timing HW as assistance for an IEEE 1588 SW implementation for use in Rohde&Schwarz FSL spectrum analyzers.